Long and short covering edges in combination logic circuits
W.-N. Li, Sudhakar M. Reddy, Sartaj K. Sahni · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990
The polynomial time algorithm obtained earlier by the authors is extended to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. It is shown how to find, in polynomial time, a minimal cardinality set MinMaxSP for a given combinational logic circuit. Combinational circuit verification is used to verify the sequential circuit delays.>