Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator
Klaus Gaedke, M. Borsum, Maximilian Georgi, A. Kluger, J.-P. Le Glanic, P. Bernard · 2007
The architecture and VLSI implementation of a programmable HD real-time motion estimator is presented. Due to the programmability, main video compression standards like MPEG-2, H.264, and VC-1 are supported. A sophisticated data flow concept in combination with a VLIW approach for controlling leads to a sustained utilization of the arithmetic resources of 95%. An area efficient architecture and design of the datapath consisting of 64 parallel processing elements reduced the required complexity to 1.2 million gates. With a first VLSI implementation in 90 nm standard cell semiconductor technology a maximum clock rate of 334 MHz was achieved. This design enables real-time motion estimation in HD format with 1920-1080 pixels at 25 Hz frame rate.