Analysis of vector access performance on skewed interleaved memory
Chuen-Liang Chen, Chung-Kai Liao · 1989
Memory interleaving and memory skewing are two hardware approaches to reduce memory access conflict for many advanced computer architectures, while pipelined vector computer covers many commercially available supercomputers. The goal of this paper is to study the vector accessing behavior on skewed interleaved memory under pipelined processing environment.