Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins · 2003
Coarse-grained reconfigurable architectures have be-come increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained recon-figurable architectures. This algorithm is a key part of our Dynamically Reconfigurable Embedded Systems Com-piler (DRESC). It is capable of solving placement, schedul-ing and routing of operations simultaneously in a modulo-constrained 3D space and uses an abstract architecture rep-resentation to model a wide class of coarse-grained archi-tectures. The experimental results show high performance and efficient resource utilization on tested kernels. 1