At-speed testing of SOC ICs
Vlado Vorisek, Thomas Koch, Hermann Fischer · 2004
This paper discusses the aspects and associated requirements of design and implementation of at-speed scan testing. It also demonstrates some important vector generation and implementation procedures based on a real design. An innovative method of scan pattern timing creation based on the results from Static Timing Analysis is pre-sented. The paper also describes the usage of a clock con-trol module on J750 tester, which creates fast clock by combining two tester channels with high edge placement accuracy. These methods allow a short test pattern preparation time and the use of low-cost test equipment, while providing the high quality at-speed testing. 1.