Architecture and design of a very fast real time delay insensitive asynchronous morphological processor in GaAs
Juan Antonio Montiel-Nelson, S. Nooshabai · 2002
Delay insensitive asynchronous design techniques are employed to implement a mathematical morphology processor in GaAs. A modified version of the DCVSL family is introduced, in order to achieve ultra-fast data rates. Simulation of the architecture implementation in GaAs MESFET 0.6 /spl mu/m Vitesse technology demonstrates the reliability of this ASIC system for high end image processing applications.