A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits
Santino Mele, Michele Favalli · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2011
This letter addresses the problem of delay fault test generation in circuits using macros whose implementation is not known. The proposed approach uses a new signal representation that allows us to evaluate any kind of sensitization conditions (robust, non-robust, and functional) by means of Boolean differential calculus. Such an approach makes use of binary decision diagrams to support the computation of sensitization conditions for each macro along a path and of Boolean satisfiability to justify such conditions at primary inputs. Results are shown for a set of benchmarks.