An efficient BIST scheme for high-speed adders
Dimitrios Nikolos, Dimitrios Nikolos, Haridimos T. Vergos, Constantinos E. Efstathiou · 2004
In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal performance penalty, small hardware overhead and the benefits of at-speed testing.