A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq
Masayuki Sanada · 2002
A CAD-based failure diagnosis technology for CMOS LSI's using abnormal Iddq has been developed to indicate the presence of physical damage in a circuit. By using set operations to compare the portions of an LSI that exhibit abnormal Iddq with the portions of an LSI that exhibit normal Iddq, this new method can progressively reduce the set of possible faulty blocks to localize a defect. To easily perform failure diagnosis, the expected input combination of each block, determined for simulation dump list of expected internal node value, is applied. This paper describes the abnormal Iddq phenomenon and the method of failure point localization using abnormal Iddq test patterns. The ISCAS'85 C17 benchmark was applied to verify this new diagnostic technique.