CAM-based single-chip shared buffer ATM switch
Kenneth J. Schultz, P. Glenn Gulak · 2002
A novel single-chip shared buffer ATM switch architecture is presented, in which a content addressable memory (CAM) is used to control access to the shared buffer RAM, in place of a linked list mechanism. The switch operation is explained in detail, and its performance is compared to that of a linked list switch. The memory capacity requirements are decreased, and cell storage and retrieval is simplified. Additional features are easily added, including priority handling and the first reported architectural support for multicasting in a single-chip shared buffer ATM switch. A novel parallel-to-serial memory is presented as an interface between the shared buffer and the output ports. Speed, area, power dissipation, and other physical performance parameters, are estimated.>