An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems
Shingo Yoshizawa, Orikasa Atsushi, Yoshikazu Miyanaga · 2011
In this paper, we propose an area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems. The proposed FFT processor is based on mixed-radix multipath delay commutator (MRMDC) architecture in terms of low complexity and high memory utilization. A conventional MRMDC FFT processor increases hardware scale due to delay commutators which are used to change the order of the input sequences. The proposed FFT processor employs pre- and post-commutators which can reduce delay elements and cooperate with other MIMO-OFDM processing blocks. The designed 128-point FFT processor reduced 49% in logic gate count and 67% in power dissipation on 90-nm CMOS technology.