Advanced DC-SF Cell Technology for 3-D NAND Flash
S. Aritome, Yoohyun Noh, Hyun-Seung Yoo, Eun Seok Choi, Han Soo Joo, Youngsoo Ahn, Byeongil Han, Sung‐Jae Chung, Keonsoo Shim, Keunwoo Lee, Sanghyon Kwak, Sung‐Chul Shin, Iksoo Choi, Sanghyuk Nam, Gyu-Seog Cho, Dongsun Sheen, Seung-Ho Pyi, Jongmoo Choi, Sung-Kye Park, Jinwoong Kim · IEEE Transactions on Electron Devices · 2013
Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories.