VLSI architecture design of a versatile variable length decoding chip for real-time video codecs
K.-M. Yang, H. Fujiwara, T. Sakaguchi, A. Shimazu · 2002
The authors describe a VLSI architecture of a versatile variable length decoder suitable for several-coding algorithms. This design can achieve real-time performance for video codecs and is based on the CCITT recommendation H.261 format. It includes an extra module to decode the variable length codes (VLC) defined by the International Organization for Standardization (ISO) Joint Photographic Experts Group (JPEG). Moreover, taking into account the fact that some VLCs used by H.261 and/or JPEG might be incorporated into the evolving ISO Moving Picture Experts Group (MPEG) algorithm, the design uses (a) PLAs for fixed VLC tables which can be shared by different algorithms and (b) content addressable memory (CAM) for downloadable tables to accommodate variations. The authors also describe a deformatter, implemented by a finite-state machine, whose function is to extract header information embedded in the coded bit-stream.>