Robust delay-fault test generation and synthesis for testability under a standard scan design methodology
Kwang-Ting Tim Cheng, Srinivas Devadas, Kurt Keutzer · 1991
One of the principal reasons that robust delay-fault testing has not been used extensively in industry is that the application of a robust test vector pair to the combinational logic portion of a VLSI sequential circuit requires that the memory elements in the circuit be enhanced scan flip flops, i.e. flip-flops that can store, not just one, but two bits of state.This is because an arbitrary vector pair may not be able to be robustly applied to a sequential circuit under a standard scan design methodology.In this paper, we address the problem of test generation for, and the synthesis of, VLSI sequential circuits that are robustly delay-fault testable under a standard scan design methodology.We present synthesis and test results on several real designs.