Energy-efficient load and store reuse
Jun Yang, Rajiv Gupta · 2001
Our experience has shown that even programs compiled using optimizing compilers contain very high levels of load and store redundancy. With the increasing importance of energy-ecient processor design, this load-store redundancy can be viewed as an opportunity for reducing on-chip cache activity and hence the energy consumed by the cache. However, taking advantage of this opportunity is a non-trivial task because a load-store reuse mechanism for removing redundancy will itself consume energy. To get an overall reduction in energy consumed we must save more energy in the cache than is consumed by the resuse mechanism. Our experiments with an aggressive redundancy removal mechanism resulted in a net increase in energy used.