Virtual fault simulation of distributed IP-based designs
Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli · 2000
Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components.In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design [1,2].As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components.