Putting it all together: using automated techniques for the design and test of large telecommunication devices
Eric-Hans Kramer, R.M. Lee · Third Annual IEEE Proceedings on ASIC Seminar and Exhibit · 2002
The design process for a large ASIC that will be used in AT&T data transmission systems is described. The design presented many challenges, including a large gate count and a short schedule. The circuitry was difficult to test both for proper functionality and for fault coverage. Many synergistic benefits were realized from the techniques employed in this process, including: (1) a heavy reliance on a C model synthesizer, (2) behavioral modeling for design verification, (3) software generation of functional tests and automatic analysis of device operation, (4) BIST and other methods for improved fault coverage and, (5) effective use of the SUN workstation. Although some of these techniques are not new, how they were combined and applied was unusual. This resulted in significant design quality and schedule improvements.>