Wrong-path instruction prefetching
Jim Pierce, Trevor Mudge · 1996
Instruction cache misses can severely limit the performance of both superscalar processors and high speed sequential machines. Instruction cache prefetching attempts to prevent misses, or at least reduce their cost, by bringing lines into the instruction cache before they are accessed by the CPU fetch unit. There have been several algorithms proposed to do this, most notably next-line prefetching and table-based target prefetching schemes. A new scheme called wrong-path prefetching is proposed which combines next-line prefetching and target-always prefetching. Surprisingly, a large part of its performance is based upon prefetching the not-taken path of conditional branches. Not only does wrong-path prefetching achieve higher performance than next-line or table-based prefetching schemes, the amount of additional hardware required is roughly the same as next-line and considerable less than table-based implementations. When compared with no prefetching, wrong-path prefetching can reduce the cache miss penalty by as much as 70%. As with all prefetching methods, performance comes at the cost of additional memory traffic. The amount of traffic generated by wrong-path prefetching is similar to that of the other schemes. 2 Wrong-Path Instruction Prefetching 1