Systolic IIR filters with bit level pipelining
Roger Woods, S.C. Knowles, John V McCanny, John G. McWhirter · 2003
A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.>