Error diagnosis for transistor-level verification
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srinivasan, David P. LaPotin · 1994
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional speci cation.The method eciently propagates mismatched p atterns from erroneous outputs backward into the network and calculates circuit regions which most likely contain the error(s).In contrast to previous approaches, the described t e chnique does not depend on a xed set of error models.Therefore, it is more general and especially suitable for transistor-level circuits, which have a broader variety of possible design errors than gate-level implementations.Furthermore, the proposed method is also applicable for incomplete sets of mismatched p atterns and hence c an be used not only as a debugging aid for formal veri cation techniques but also for simulationbased approaches.Experiments with industrial CMOS circuits show that for most design errors the identi ed problem region is less than 3% of the overall circuit.