iiQueue, a QoS-oriented queue module for input-buffered ATM switches
Sung Mo Kang, Haofan Duan, John W. Lockwood, J.D. Will · 2002
This paper discusses the principle of a versatile, 3-dimensional queue (3DQ) and its prototype implementation-illinois input Queue (iiQueue) module for input-buffered ATM switches. 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per virtual connection Quality-of-Service (QoS) and avoids Head-Of-Line (HOL) blocking. Implemented with field programmable gate array (FPGA) devices for the core 3DQ logic on a 6-layer printed circuit board (PCB), iiQueue prototype module can process ATM cells at 622 Mb/s (OC-12). With multichip module (MCM) and fast GaAs logic implementation, iiQueue module is expected to process cells at 2.5 Gb/s (OC-48).