Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor
Tadahiko Nishimukai, Hideo Inayoshi, K. Takagi, K. Iwasaki, Ikuya Kawasaki, M. Hanawa, Takashi Okada · 2003
A stack cache scheme in combination with a general register set is presented as an alternative to the register file. Two cache memories, a 1-K byte code cash and a four-entry cache for branch instructions, are also embedded to accelerate the pipeline stream. This scheme has been implemented and evaluated on a 32-bit microprocessor, the Hitachi H32/200, based on TRON (The Real-time Operating system Nucleus) specifications. This processor contains 730 K transistors in 1.0- mu m CMOS. It performs 6 to 7 MIPS (million instruction per second) at a 20-MHz clock rate.>