A 60 ns access 32 kByte 3-transistor flash for low power embedded applications
Tamio Ikehashi, Jun-ichiro Noda, K. Imamiya, M. Ichikawa, A. Iwata, Takuya Futatsuyama · 2002
In this paper, we present a new memory, 3-transistor flash (3-Tr), which is suited to the embedded application. The memory cell has inherited low power the erase/program characteristic of the NAND flash. The cell size of the 32kByte 3-Tr flash, fabricated in a 0.4um NAND flash technology, is 4.36 /spl mu/m/sup 2/. This is about 1/8 of the EEPROM cell size having the same design rule. We also propose two circuit technologies, a low power sensing scheme and a double stage boosting scheme (DSB). The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during the program mode. It is also immune to a decrease of the supply voltage Vdd.