Design of 32-bit RISC processor and efficient verification
Geun-young Jeong, Ju-sung Park · Korea-Russia International Symposium on Science and Technology · 2003
The design and verification of a 32-bit general- purpose microprocessor, which is compatible with ARM? RISC core, is described. In the architectural point of view, the processor has 3-stage pipeline, 6 register banks, 32-bit ALU, and 4-cycle MAC. The core described here was designed by latch base for low power and low complexity. Its functional operation was verified by comparison the results of logic simulation with those of the commercial simulator. Each instruction and its random combinations were all tested. The core was implemented by FPGA to check its proper operation for various applications, such as ADPCM (G.721-speech coding), SOLA (voice speed variation), MP3 decoding. It carried out successfully those algorithms.