On the bandwidth availability of multistage interconnection networks
Andreas A. Veglis, A. Pombortsis · 2002
In this paper, we develop a model that describes the behaviour of a multistage interconnection network (MIN) interconnecting processors and memory modules, when faults exist among the functional units (the processors, memory modules, switching elements and links). Based on this model, we compare the performability of various MIN systems that employ extra stages, or multiple disjoint copies of MINs vertically stacked.>