CoreRacer
Gilles Pokam, Cristiano L. Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Gottschlich, Jung-Woo Ha, Youfeng Wu · 2011
Shared memory multiprocessors are difficult to program because of the non-deterministic ways in which the memory operations from different threads interleave. To address this issue, many hardware-based memory race recorders have been proposed that efficiently log an ordering of the shared memory interleavings between threads for deterministic replay. These approaches are challenging to integrate into current processors because they change the cache subsystem or the coherence protocol, and they mostly support a sequentially consistent memory model.