Verification of register transfer level (RTL) designs
Alberto Palacios Pawlovsky, Sachio Naito · 1991
The authors' verification method is based on the translation of the specification and design representation to graph models, where the nodes and edges have a symbolic representation. These labeled graphs are then simplified and by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding one in the design.>