HARDWARE ACCELERATION ALONE WILL NOT MAKE FAULT GRADING ULSI A REALITY
Gopi Ganapathy, Jacob A. Abraham · 2005
A low cost deterministic fault simulation technique for practical ultra large scale integrated WSI) circuits, in a hardware accelerator environment is presented. A dynamic test directed partitioning scheme is implemented to select the faults which should be deterministically simulated for a given pattern. Experimental data show a speedup greater than an order of magnitude over conventionad fault simulation.