A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing
S. Narita, Koji Ishibashi, S. Tachibana, K. Norisue, Y. Shimazaki, J. Nishimoto, Kota Uchiyama, T. Nakazawa, K. Hirose, I. Kudoh, R. Izawa, S. Matsui, S. Yoshioka, Masataka Yamamoto, Ikuya Kawasaki · 2002
A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition.