An 80-MFLOPS (peak) 64-b microprocessor for parallel computer
Hiraku Nakano, M. Nakajima, Yasuhiro Nakakura, T. Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hideki Kadota · IEEE Journal of Solid-State Circuits · 1992
An 80-MFLOPS (peak) 64-b microprocessor that employs superscalar architecture to execute two instructions simultaneously in one 25-ns cycle, including the combination of 64-b floating-point add and multiply instructions, is described. The processor implemented in a 0.8- mu m CMOS technology contains 1300 K transistors. The processor also employs a RISC architecture and Harvard-style bus organization. The authors provide an overview of the processor, especially focusing on processor architecture, floating-point hardware, and performance.>