Low-Complexity Triple-Error-Correcting Parallel BCH Decoder
Jaewoong Yeon, Seung-Jun Yang, Cheol‐Ho Kim, Hanho Lee · JSTS Journal of Semiconductor Technology and Science · 2013
This paper presents a low-complexity triple-error-correcting parallel Bose?Chaudhuri? Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-bystep (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multiparallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4- parallel (1020, 990) BCH decoder over GF(212), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.