A 70 nm 16 Gb 16-Level-Cell NAND flash Memory
Noboru Shibata, H. Maejima, Katsuaki Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, Tatsuo Shimizu, M. Honma, S. Hoshi, T. Kawaai, Kazunori Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, Tomonori Takahashi, Toshifumi Shano, Yuto Komatsu, Katsushi Nagaba, Mitsuhiko Kosakai, Norikazu Motohashi · IEEE Journal of Solid-State Circuits · 2008
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.