A parallel SRT divider for systolic linear system solvers
H.A. Nienhaus, C. Monemi · 2003
The design and simulation results for a CMOS parallel SRT divider which produces a 16-bit quotient from a 16-bit floating-point dividend and a 16-bit floating-point divisor are described. The divider used mixed-radix signed-digit numbers for the quotient before decoding. A behavioral simulator which implements the detailed algorithms, has been written for the divider in C. Simulation results have been compared to computer division for 1000 random test vectors. Timing simulations using the simulator FACTS give worst-case propagation delays of 326.5 ns using 3- mu m CMOS parametric data.>