The design of a systolic architecture to implement graphic transformations
Giorgos M. Papadourakis, George N. Bebis · 2002
A new systolic graphic array architecture is proposed in order to achieve the high computational throughput necessary to generate real-time processing. The proposed systolic architecture implements graphic transformations such as translations, scaling, and rotations on three dimensional vertices. The logarithmic number system is utilized to further increase the computational throughput. A comparison between the proposed systolic architecture and the Weitek 7100 SME graphic processor in terms of speed is performed.>