Using a reconfigurable compute cluster for the acceleration of neural networks
Christopher Pohl, Jens Hagemeyer, Johannes Romoth, Mario Porrmann, Ulrich Rückert · 2009
In this paper we present the RAPTOR family as an advanced modular platform for both FPGA-based rapid prototyping and hardware acceleration. Using modern FPGAs and high speed communication links, performance and flexibility of the approach will be shown by means of Kohonens self-organizing map algorithm. This highly parallel algorithm is partitioned onto several FPGAs in different system environments, such as to demonstrate the scalability and the flexibility of the proposed platforms.