A 16-Core Processor With Shared-Memory and Message-Passing Communications
Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Yu Zheng, Maofei He, Jiajie Zhang, Ying Yan, Haofan Yang, Jun Shu Han, Xu Cheng, Zhang Zhang, Minge Jing, Xiaoyang Zeng · IEEE Transactions on Circuits and Systems I Regular Papers · 2013
A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 × 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 mm2and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H.264 decoder and an LTE channel estimator.