Design and FPGA Verification of Dual-Speed Adaptive Ethernet Controller
Min Qian, Jing Zhu, Yunpeng Cao, Yang Cui-jun · 2011
The embedded Ethernet is widely applied, and its research is very important. In this paper, the embedded Ethernet controller is designed. The Ethernet MAC sublayer protocol and the architecture of Ethernet data frame are briefly introduced. The 10/100Mbps adaptive Ethernet controller is designed with Verilog-HDL, which includes the WISHBONE bus interface, Tx/Rx module, flow control module, etc. The testing vectors are constructed and the whole design is simulated in ModelSim PLUS 6.4SE tools and successfully verified by ALTERA FPGA. The result of logic simulation and FPGA physical verification of board level indicate that the related function of 10/100Mbps adaptive Ethernet controller is realized.