Block-level fault isolation using partition theory and logic minimization techniques
C.‐J. Richard Shi · 2002
Multichip modules are emerging as a key packaging technology for mixed-signal circuits and systems. In this paper, we consider how to localize a failure within a chip boundary as rapidly as possible in order to expedite the rework process and to minimize its overall impact on manufacturing throughput and cycle time. A key contribution of this paper is to provide a unified block-level fault isolation framework for analog and digital circuits, and to show that optimum fault isolation reduces to set covering. This allows us to apply directly powerful set covering techniques and solvers developed recently in logic minimization. In addition, we present a greedy peeling heuristic with performance bound computation. Some preliminary experimental results are included to demonstrate the feasibility and performance of the proposed approach.