A 0.8 W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback
H. Yamauchi, Y. Matsushita, Shigeyuki Okada, K. Taketa, Yoshio Matsuda, T. Mori, Shinichiro Okada, T. Watanabe, Y. Harada, M. Matsudaira · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2002
A HDTV video processor with decoding/display of two MPEG MP@HL streams and reverse playback with smooth 30 frames/s without frame skip uses a 0.18 /spl mu/m 5-layer process in 6.86/spl times/6.86 mm/sup 2/ and 5.7M transistors. It is for home multimedia and mobile TV applications. It operates at 135 MHz and 0.8 W at 1.8 V.