Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures
Dionysios I. Reisis, Nikolaos Vlassopoulos · IEEE Transactions on Circuits and Systems I Regular Papers · 2008
Speeding up fast Fourier transform (FFT) computations is critical for today's real-time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures, this paper presents an address generation technique which enables a radix-bprocessor to access in parallelbmemory banks without conflicts during each stage's computations. Usingkbmemory banks at each stage leads to increasing the speedup of the algorithm by a factor ofkb. The address generation can be realized in each radix-bstage by the use of lookup tables of sizeO(kb2) bits. The proposed technique is cost efficient and leads to the design of FFT architectures of high speedup and high sustained throughput.