Fault simulation with PLDs
W.L. Gallagher, H.H. Yao, Earl E. Swartzlander · 2002
One measure of the effectiveness of fault tolerance in a circuit is fault coverage, the ratio of the number of faults detectable or correctable to the number of possible faults. Fault simulation can provide an estimate of the fault coverage, but is often prohibitively slow if performed in software. Simulating a faulty circuit using programmable logic devices can speed up the process. Two basic approaches to fault simulation using PLDs are discussed. Fault simulation, for ripple carry adders is carried out in both a PLD and wholly in software and the performance compared.