M-sequence based M-ary/SS scheme for high bit ratetransmission in DS/CDMA systems
Takumi Ito, Seiichi Sampei, Norihiko Morinaga · Electronics Letters · 2000
A high bit rate and high power efficiency transmission scheme is proposed which uses an M-sequence based M-ary/SS scheme for DS/CDMA systems combined with a block branch metric calculation for the Viterbi decoder and a signal to noise plus interference power ratio (SNIR) measurement scheme for transmitter power control (TPC). Computer simulation confirms that the proposed scheme leads to a much higher BER performance while maintaining a lower peak to average transmitter power ratio.