A dual-core programmable decoder for LDPC convolutional codes
Marcos B. S. Tavares, Emil Matúš, Steffen Kunze, Gerhard Paul Fettweis · 2008
We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tail-biting LDPC convolutional codes. This architecture has a very good scalability and is fully programmable so that it can be applied to several communications and data storage scenarios. The synthesis results show relatively small area consumption for very high decoding speeds.