A 48-core IA-32 processor with on-die message-passing and DVFS in 45nm CMOS
Jason Howard · 2010
This paper describes a microprocessor that integrates 48 IA-32 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 6 × 4 2 D-mesh network-on-chip topology. Located at each mesh node is a five-port packet-switched router shared between two cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1V supply, cores operate at 1 GHz and the 2 D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The 567 mm2processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors.