Design architecture of generic DFT/DCT 1D and 2D engine controlled by SW instructions
Hanan M. Hassan, Ahmed F. Shalash, Hisham M. Hamed · 2010
In this paper, a hardware implementation for generic DFT/IDFT DCT/IDCT 1D (N-point) and 2D (N × M point) processor is proposed, as N/M in the form of 2x× 3yto support different communication and signal processing applications. An in-place bank of 2 N-word dual-port memories with a continuous address generator is adopted to accommodate high-speed applications. This engine is controlled by software instructions running on a simple embedded processor to provide more flexibility in switching between different modes and desired number of points, instead of a complex hardware controller. This software flexibility also allows the user to adapt the operations on data to match his needs.