Modeling the interconnects of Xilinx Virtex FPGAs and derivation of their test configurations
Christian Giasson, Xiaoling Sun · 2004
The paper employs bipartite graphs to model the local interconnect resources of Xilinx Virtex field programmable gate arrays (FPGAs). A computer algorithm is introduced to derive a minimal or near minimal set of test configurations (TCs) by solving edge coloring problems of the graphs, where each color represents a TC. A minimal set of 26 TCs was obtained for Virtex FPGAs.