Mapping to reduce contention in multiprocessor architectures
Loren Schwiebert, D.N. Jayasimha · 2002
Reducing communication overhead has been widely recognized as a requirement for achieving efficient mappings which substantially reduce the execution time of parallel algorithms. This paper presents an iterative heuristic for static mapping of parallel algorithms to architectures. Special attention is given to measuring and reducing channel contention. Experimental results are used to show the effects of channel contention for packet-switched networks and the improvement realized by the authors' heuristic. They also present preliminary results for wormhole-routed networks.>