Bit-serial test pattern generation by an accumulator behaving as a non-linear feedback shift register
Giorgos Dimitrakopoulos, Dimitrios Nikolos, Dimitris Bakalis · 2003
Arithmetic function modules which are available in many circuits can be utilized to generate test patterns and compact test responses. Recently, it was shown that an adder or an accumulator cannot be used as a bit serial test pattern generator due to the poor random properties of the generated sequences. Thus, accumulator-multiplier or adder-multiplier structures have been proposed In this paper we show that an accumulator behaving, in test mode, as a non-linear feedback shift register (NLFSR) can be used efficiently for bit serial test pattern generation. A hardware as well as a software implementation of the proposed scheme is given The efficiency of the proposed scheme is verified by comparing it against LFSR and other arithmetic function based bit serial test pattern generators.