Embedded RAM test using flag‐scan register
H. Maeno, Shuuhei Iwade, Shimpei Kayano, Masayoshi Sakao · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 1994
Abstract New test methods and a test circuit for the testing of embedded RAMs on ASICs are proposed. These test methods are based on the scan path method, and a new scan register, called Flag‐Scan Register, which is dedicated to RAM test, has been developed for the test methods. Also, high‐speed testing is possible by using exhaustive pseudorandom addressing. Furthermore, the methods have been applied to gate array‐based RAMs and the effectiveness has been verified.