Delay testing using a matrix of accessible storage elements
P. Varma, Tushar R. Gheewala · 2002
This paper discusses a delay test methodology that avoids the area and performance overhead of enhanced scan elements by using a matrix of accessible storage elements. Delay test generation is performed for circuits, which may contain internal tri-state elements, bi-directional ports, asynchronous sets/resets and clock gating, using an automatic test pattern generator that is based on an extended 16 valued calculus.>